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TERMINOLOGY

The term ''EDA'' is also used as an umbrella term for Computer-aided Engineering , Computer-aided Design and Computer-aided Manufacturing of Electronics in the discipline of Electrical Engineering . This usage probably originates in the IEEE Design Automation Technical Committee.

This article describes EDA specifically for electronics, and concentrates on EDA used for designing Integrated Circuits . The segment of the industry that must use EDA are chip designers at semiconductor companies. Large chips are too complex to design by hand.


GROWTH OF EDA

EDA for electronics has rapidly increased in importance with the continuous scaling of Semiconductor technology. (See Moore's Law .) Some users are Foundry operators, who operate the Semiconductor Fabrication facilities, or "fabs", and design-service companies who use EDA software to evaluate an incoming design for manufacturing readiness. EDA tools are also used for programming design functionality into FPGA s.


HISTORY

Before EDA, integrated circuits were designed by hand, and manually laid out. Some advanced shops used geometric software to generate the tapes for the Gerber Photoplotter , but even those copied digital recordings of mechanically-drawn components. The process was fundamentally graphic, with the translation from electronics to graphics done manually. The best known company from this era was Calma , whose GDSII format survives.

By the mid-70s, developers were starting to automate the design, and not just the drafting. The first placement and routing tools were developed. The proceedings of the Design Automation Conference cover much of this era.

The next era began more or less with the publication of "Introduction to VLSI Systems" by Carver Mead and Lynn Conway in 1980 . This groundbreaking text advocated chip design with programming languages that compiled to silicon. The immediate result was a hundredfold increase in the complexity of the chips that could be designed, with improved access to design verification tools that used logic simulation. Often the chips were not just easier to lay out, but more correct as well, because their designs could be simulated more thoroughly before construction.

The earliest EDA tools were produced academically, and were in the public domain. One of the most famous was the "Berkeley VLSI Tools Tarball", a set of UNIX utilities used to design early VLSI systems.

Another crucial development was the formation of MOSIS , a consortium of universities and fabricators that developed an inexpensive way to train student chip designers by producing real integrated circuits. The basic idea was to use reliable, low-cost, relatively low-technology IC processes, and pack a large number of projects per wafer, with just a few copies of each projects' chips. Cooperating fabricators either donated the processed wafers, or sold them at cost, seeing the program as helpful to their own long-term growth.

1981 marks the beginning of EDA as an industry. For many years, the larger electronic companies, such as Hewlett Packard , Tektronix , and Intel , had pursued EDA internally. In 1981, managers and developers spun out of these companies to concentrate on EDA as a business. Daisy Systems , Mentor Graphics , and Valid Logic Systems were all founded around this time, and collectively referred to as DMV. Within a few years there were many companies specializing in EDA, each with a slightly different emphasis.

In 1985 , Verilog , a popular high-level design language, was first introduced as a hardware description language by Gateway. In 1987 , the U.S. Department of Defense funded creation of VHDL as a specification language. Simulators quickly followed these introductions, permitting direct simulation of chip designs: executable specifications. In a few more years, back-ends were developed to perform logic synthesis.

Many of the EDA companies acquire small companies with software or other technology that can be adapted to their core business. Most of the market leaders are rather incestuous amalgamations of many smaller companies. This trend is helped by the tendency of software companies to design tools as accessories that fit naturally into a larger vendor's suite of programs (the "tool flow").

While early EDA focused on Digital Circuitry , many new tools incorporate analog design, and mixed systems. This is happening because there is now a trend to place Entire Electronic Systems On A Single Chip .

Current digital flows are extremely modular (see Integrated Circuit Design , Design Closure , and Design Flow (EDA) ). The front ends produce standardized design descriptions that compile into invocations of "cells,", without regard to the cell technology. Cells implement logic or other electronic functions using a particular integrated circuit technology. Fabricators generally provide libraries of components for their production processes, with simulation models that fit standard simulation tools. Analog EDA tools are much less modular, since many more functions are required, they interact more strongly, and the components are (in general) less ideal.


PRODUCT AREAS

EDA is divided into many (sometimes overlapping) sub-areas. They mostly align with the path of manufacturing from design to mask generation. The following applies to chip/ASIC/FPGA construction but is very similar in character to the areas of printed circuit board design:

  • s, output in Verilog , VHDL , SPICE and other formats.

  • Floorplanning : The preparation step of creating a basic die-map showing the expected locations for logic gates, power & ground planes, I/O pads, and hard macros. (This is analogous to a city-planner's activity in creating residential, commercial, and industrial zones within a city block.)

  • -description (often specified via a hardware description language, or "HDL", such as Verilog or VHDL) into a discrete netlist of logic-gate ( Boolean -logic) primitives.

  • Behavioral Synthesis , High Level Synthesis or Algorithmic Synthesis : This takes the level of abstraction higher and allows automation of the architecture exploration process. It involves the process of translating an abstract behavioral description of a design to synthesizeable RTL. The input specification is in languages like behavioral VHDL, algorithmic SystemC, C++ etc and the RTL description in VHDL/Verilog is produced as the result of synthesis.

  • IP Core s: provide pre-programmed design elements.

  • EDA Database s: databases specialized for EDA applications. Needed since historically general purpose DBs did not provide enough performance.

  • Simulation : simulate a circuit's operation so as to verify correctness and performance.

  • --- Transistor Simulation – low-level transistor-simulation of a schematic/layout's behavior, accurate at device-level.

  • --- RTL Simulation – digital-simulation of an RTL or gate-netlist's digital (boolean 0/1) behavior, accurate at boolean-level.

  • --- Behavioral Simulation – high-level simulation of a design's architectural operation, accurate at cycle-level or interface-level.

  • --- Hardware Emulation – Use of special purpose hardware to emulate the logic of a proposed design. Can sometimes be plugged into a system in place of a yet-to-be-built chip; this is called '''in-circuit emulation'''.

  • , but these checks/tools specialise in detecting and reporting potential issues like data loss, Meta-stability due to use of multiple clock domains in the design.

  • ) cannot occur.

  • Equivalence Checking : algorithmic comparison between a chip's RTL-description and synthesized gate-netlist, to ensure functional equivalency at the ''logical'' level.

  • Power Analysis And Optimization : optimizes the circuit to reduce the power required for operation, without affecting the functionality.

  • of logic-gates and other technology-mapped components of the synthesized gate-netlist, then subsequent Routing of the design, which adds wires to connect the components' signal and power terminals.

  • Static Timing Analysis : Analysis of the timing of a circuit in an input-independent manner, hence finding a worst case over all possible inputs.

  • Transistor layout: (for analog/mixed-signal devices), sometimes called ''polygon pushing'' – a prepared-schematic is converted into a layout-map showing all layers of the device.

  • Design For Manufacturability : tools to help optimize a design to make it as easy and cheap as possible to manufacture.

  • Design Closure : IC design has many constraints, and fixing one problem often makes another worse. Design closure is the process of converging to a design that satisfies all constraints simultaneously.

  • Analysis of Substrate Coupling .

  • Physical Verification , PV: checking if a design is physically manufacturable, and that the resulting chips will not have any function-preventing physical defects, and will meet original specifications.

  • --- Design Rule Checking , DRC – checks a number of rules regarding placement and connectivity required for manufacturing.

  • --- Layout Versus Schematic , LVS – checks if designed chip layout matches schematics from specification.

  • --- Layout Extraction , RCX – extracts Netlist s from layout, including parasitic resistors (PRE), and often capacitors (RCX), and sometimes inductors, inherent in the chip layout.

  • Photomask used to physically manufacture the chip.

  • --- Resolution Enhancement Techniques , RET – methods of increasing of quality of final Photomask .

  • --- Optical Proximity Correction , OPC – up-front compensation for Diffraction and Interference effects occurring later when chip is manufactured using this mask.

  • --- Mask Generation – generation of flat mask image from hierarchical design.

  • Manufacturing Test

  • --- Automatic Test Pattern Generation , ATPG – generates pattern-data to systematically exercise as many logic-gates, and other components, as possible.

  • --- Built In Self Test, BIST – installs self-contained test-controllers to automatically test a logic (or memory) structure in the design

  • --- Design For Test , DFT – adds logic-structures to a gate-netlist, to facilitate post-fabrication (die/wafer) defect testing.



LARGEST COMPANIES AND THEIR HISTORIES

In 1981 , 3 managers left Tektronix , to found Mentor Graphics . Daisy Systems was founded largely by folks from Intel , and Valid Logic Systems by designers from Lawrence Livermore National Laboratory and Hewlett Packard .
At the time, analysts categorized these companies as a niche within the “computer aided design” market, primarily mechanical design drafting tools for conceptualizing bridges, buildings and automobiles. In a few years these fields diverged, and today no companies specialize in both mechanical and electrical design automation.

Cadence Design Systems was founded in the mid 80s, specializing in physical IC design. Synopsys was founded about the same time frame to productize Logic Synthesis . Both have grown to be the largest full line suppliers of EDA tools. Magma Design Automation was founded in 1997 to take advantage of the simplifications possible by building an IC design system from scratch.

In 1994 , Zuken Inc. in Japan was merged with Racal -Redac Ltd., an UK based subsidiary of Racal Electronics plc to form Zuken-Redac. It became one of the largest market share holder in the PCB design software market. Zuken -Redac was later renamed as Zuken Inc. after another merger with Incases Engineering Gmbh in 2000 .


SEE ALSO



EXTERNAL LINKS



Open source EDA tools



REFERENCES

  • http://www.staticfreesoft.com/documentsTextbook.html Computer Aids for VLSI Design by Steven M. Rubin - text is available on line

  • ''Electronic Design Automation For Integrated Circuits Handbook'', by Lavagno, Martin, and Scheffer, ISBN 0849330963 A two volume book surveying the field of EDA for ICs.